搜索资源列表
vhdl
- 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
dcdlab3
- 数字部件设计，verylog，实现用D-FLIP FLOP 实现计数器功能。-Digital Component Design, verylog, using D-FLIP FLOP realize Counter.
jk-ff
- j-k flip flop implementation in XCS2-j-k flip flop implementation in XCS200
jkff
- JK flip-flop is implemented using VHDL
vhdl_jk
- 本程序通过使用vhdl语言描述JK触发器，实现了JK触发器的四个工作状态，进而我们可以将其应用到其他使用JK触发器的电路中-The procedure by using vhdl language to describe the JK flip-flop, JK flip-flop realized the four working state, then we can apply it to others using the JK flip-flop circuit
hdl
- cnt_top,It is used to realize a D flip flop. it is written with verilog.
DtoJK
- Using an edge triggered D flip-flop to implement a JK flip-flop
5
- Code for JK flip flop and SR flip flop
cnt8
- 用JK-flip-flop做的8进制counter-mod-8-counter
srandDflipflop
- this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for e
74hc74
- 带使能和清零端的D触发器，Verilog实现，有实验说明文档。-With a clear end to enable and D flip-flop, Verilog implementation, there is experimental documentation.
D_latch
- 周立功 ACTEl FPGA做的一个D触发器程序-ZLG ACTEl FPGA program to do a D flip-flop
count10
- 十进制计数器 自己尝试编辑的，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can-Decimal counter his attempt to edit, and can-jk flip-flop, try to edit their own, using state machine to achieve, you can
vhdl-code-for-jk-flip-flop
- vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
D-flip-flop
- Verilog的简单D触发器设计-Simple D flip-flop in Verilog design
flip-flop
- Set Reset Flip Flop designed using cross coupled nand gates
The-D-flip-flop
- D触发器的Verilog硬件语言实现，开发环境是ModelSim-The D flip-flop of the Verilog hardware language development environment is ModelSim
D-flip-flop
- D 触发器的描述 寄存器的行为 描述 -D flip-flop registers describe the behavior described in the behavior described register
JK-flip-flop
- 带有异步置位复位端的上升沿触发的JK触发器，使用VHDL语言实现的-Asynchronous reset terminal set with rising edge triggered JK flip-flop, the use of VHDL language